High performance sub-system design and assembly

ABSTRACT

A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another. The first integrated circuit chips have interchip interface circuits connected each other to selectively communicate between internal circuits of the each other integrated circuit chips or test interface circuits, connected to the internal circuits of each integrated circuit chip to provide stimulus and response to said internal circuits during testing procedures. A mode selector receives a signal external to the chip to determine whether the communication is to be with one of the other connected integrated circuit chips or in single chip mode, such as with the test interface circuits. ESD protection is added to the mode selector circuitry.

[0001] This application is a Continuation-in-Part of Ser. No.09/729,152, filed on Dec. 4, 2000, which is a Divisional application of09/258,911 filed on Mar. 1, 1999, now issued as U.S. Pat. No. 6,180,426.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to structures and methods of assembly ofintegrated circuit chips into interconnected multiple chip modules. Moreparticularly, this invention relates to multiple chip structuresconnected physically and electrically.

[0004] 2. Description of the Related Art

[0005] The manufacture of embedded Dynamic Random Access Memory (DRAM)requires that process parameters that enhance the performance of thelogic or the DRAM, if separately formed on semiconductor chips, becompromised when DRAM is embedded into an array of logic gates on thesame semiconductor chip. This compromise has limited the application ofembedded DRAM. If there is no compromise in the process parameters toenhance the performance of logic or the embedded DRAM, the manufacturingprocess becomes very complicated and costly. Moreover, because of thestructure of the embedded DRAM and the logic, burn-in of the embeddedDRAM is not possible and embedding of DRAM with logic is not a reliabledesign solution.

[0006] A multiple chip module structure is a viable alternative toembedded DRAM. With multiple chips connected in intimate contact, theprocess parameters that maximize the performance of the DRAM chip andthe logic gates can be applied during manufacture. Refer to FIG. 1 for adescription of a “chip-on-chip” structure 100. Such a “chip-on-chip”structure is described in U.S. Pat. No. 5,534,465 (Frye et al.). A firstintegrated circuit chip 105 is attached physically and electrically to asecond integrated circuit chip 110 by means of an area array of solderbumps 115. The process of forming an area array of solder bumps 115 iswell known in the art and is discussed in Frye et al. 465. The secondchip 110 is then secured physically to a substrate 120. Electricalconnections 125 between the second integrated circuit chip 110 andexternal circuitry (not shown) are created as either wire bonds or tapeautomated bonds. The module further has a ball grid array 130 to securethe structure to a next level of packaging containing the externalcircuitry. Generally, an encasing material 135 is placed over the“chip-on-chip” structure 100 to provide environmental protection for the“chip-on-chip” 100.

[0007] U.S. Pat. No. 5,481,205 (Frye et al.) teaches a structure formaking temporary connections to integrated circuit chips having “solderbumps” or connection structures such as ball grid arrays. The temporaryconnections allow temporary contacting of the integrated circuit chipduring testing of the integrated circuit chip.

[0008] The handling of wafers from which the integrated circuit chipsare formed and the handling of the integrated circuit chips themselvescauses the integrated circuit chips to be subjected to electrostaticdischarge (ESD) voltages. Even though connections between the firstintegrated circuit chip 105 and the second integrated circuit chip 110are relatively short and under normal operation would not be subjectedto ESD voltages, ESD protection circuitry is required to be formedwithin the interchip interface circuit to provide protection ornecessary driving capacity for the first integrated circuit chip 105 andthe second integrated circuit chip 110 during burn-in and othermanufacturing monitoring processes.

[0009] U.S. Pat. No. 5,731,945 and U.S. Pat. No. 5,807,791 (Bertin etal.) teach a method for fabricating programmable ESD protection circuitsfor multichip semiconductor structures. The interchip interface circuiton each integrated circuit chip is formed with an ESD protection circuitand a switch to selectively connect the ESD protection circuit to aninput/output pad. This allows multiple identical chips to beinterconnected and redundant ESD protection removed.

[0010] The circuits at the periphery of integrated circuit chipsgenerally are specialized to meet the requirements of standardizedspecifications. These include relatively high current and voltagedrivers and receivers for communicating on relatively long transmissionline media. Alternately, as shown in U.S. Pat. No. 5,461,333 (Condon etal.) the interface may be differential to allow lower voltages on thetransmission line media. This requires two input/output pads fortransfer of signals.

[0011] U.S. Pat. No. 5,818,748 (Bertin et al.) illustrates a separationof chip function onto separate integrated circuits chips. This allowsthe optimization of the circuits. In this case, EEPROM is on oneintegrated circuits chip and drivers and decoders are on another. Thechips are placed face to face and secured with force responsiveself-interlocking micro-connectors.

[0012]FIGS. 2a and 2 b show multiple “chip-on-chip” structures 100constructed on a wafer. Not shown is the forming of the first integratedcircuit chip on a silicon wafer. The first integrated circuit chip istested on the wafer and nonfunctioning chips are identified. The waferis separated into the individual chips. The functioning first integratedcircuit chips 105 then are “flip-chip” mounted on the second integratedcircuit chip 110 on the wafer 200. The wafer 200 is then separated intothe “chip-on-chip” structures 100. The “chip-on-chip” structures 100 arethen mounted on the modules as above described.

SUMMARY OF THE INVENTION

[0013] An object of this invention is to provide a multiple integratedcircuit chip structure where the interchip communication betweenintegrated circuit chips of the structure have no ESD protectioncircuits and no input/output circuitry. The interchip communication isbetween internal circuits with a minimal electrical load.

[0014] Another object of this invention is to provide a circuit toselectively connect internal circuits of the integrated circuits to testinterface circuits having ESD protection circuits and input/outputcircuitry designed to communicate with test systems during assembly andtest.

[0015] A further object of the invention is to provide a circuit toselectively connect internal circuits of the integrated circuits to oneof two paths, either for single chip mode operation or for multi-chipmode operation.

[0016] To accomplish these and other objects, a multiple interconnectedintegrated circuit chip structure has a first integrated circuit chipphysically and electrically connected to one or more second integratedcircuit chips. The integrated circuit chips may be connected to oneanother by means of an area array of solder bumps. The first integratedcircuit chip has interchip interface circuits connected to the one ormore second integrated circuit chips to communicate between internalcircuits of the first and second integrated circuit chips and testcircuits. The test circuits are connected to the internal circuits ofthe first integrated circuit chip to provide stimulus and response tothe internal circuits during testing procedures. Additionally, the firstintegrated circuit chip can be set to be operated in single chip mode,if desired.

[0017] The second integrated circuit chips have input/output interfacecircuitry to communicate with external circuitry connected to the secondintegrated circuit chips and to protect the second integrated circuitchips from electrostatic discharge voltages. Further, the secondintegrated circuit chips have interchip interface circuits connected tothe first integrated circuit chip and to each other to communicatebetween the internal circuits of the chips and with test circuits. Thetest circuits are connected to the internal circuits of the secondintegrated circuit chips to provide stimulus to and response from theinternal circuits during testing and burn-in procedures.

[0018] The interchip interface circuitry has an internal interfacecircuit for transferring electrical signals between the internalcircuits of one integrated circuit chip to another integrated circuitchip. The interchip interface circuitry further has a mode select switchto selectively connect between the internal circuits of one integratedcircuit chip and another integrated circuit chip or to operate in singlechip mode, including stand-alone operation or connection to testinterface circuits. The mode select signal to the mode switch isexternal to the chip. The signal may come from another of the integratedcircuit chips, from the substrate, or from a test interface, or otherexternal source. The mode switch has three terminals and a controlterminal. The first terminal is connected to an output of the internalinterface circuit, a second terminal connected to the internalcircuitry, and the third terminal connected to an input/outputinterface. A mode selector is connected to the control terminal. Thestate of the mode selector determines the connection between the firstterminal and thus the output of the internal interface circuit, thesecond terminal and thus the internal circuitry, and the third terminaland thus the test interface or other interface. During multi-chip modeoperation, the first terminal is connected to the second terminal suchthat the internal circuits of two integrated circuits are connectedthrough their respective internal interfaces. During single chip modeoperations, the internal circuits are connected to an input/outputinterface. For example, during test and burn-in, the input/outputinterface may connect to external testing circuitry.

[0019] The first integrated circuit chip could be fabricated using afirst type of semiconductor process and the second integrated circuitchip would be fabricated with a second type of semiconductor processthat is not compatible with the first type of semiconductor process, andso on. As an example, the first integrated circuit chip could be anarray of memory cells and the second integrated circuit chip wouldcontain electronic circuitry formed with a process not compatible with aprocess of the array of memory cells. Alternatively, the secondintegrated circuit chip is an array of memory cells and the firstintegrated circuit chip contains electronic circuitry formed with aprocess not compatible with a process of the array of memory cells.Other integrated circuit chips could be fabricated in other ways.Fabricating the first integrated circuit chip using its optimumsemiconductor process, fabricating the second integrated circuit chipusing its optimum semiconductor process, and then joining the first andsecond integrated circuit chips by this invention creates a multiplechip integrated circuit structure having maximum performance withminimum cost.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 shows a cross-sectional view of a “chip-on-chip” structureof the prior art.

[0021]FIGS. 2a and 2 b are respectively top view and a cross-sectionalview of a “chip-on-chip” structure formed on a-semiconductor wafer ofthe prior art.

[0022]FIG. 3 is a cross-sectional view of a “chip-on-chip” structure,schematically the circuitry contained on each chip of the chip-on-chipstructure of this invention.

[0023]FIGS. 4a-d are schematics of the interchip interface circuits ofthis invention.

[0024]FIGS. 5a and 5 b are schematic drawings of an embodiment of theinterchip interface of this invention.

[0025]FIGS. 5c and 5 d are schematic drawings of an alternativeembodiment of the interchip interface of this invention.

[0026]FIGS. 6a and 6 b are top surface views of the first and secondintegrated circuit chips of FIG. 3 showing test pads and interchipinput/output pads of this invention.

[0027]FIGS. 7a through 7 d are examples of multiple chip modules thatcould be made using the process of this invention.

DETAILED DESCRIPTION OF THE INVENTION

[0028] The process and structure of the present invention can beextended to any kind of format of multi-chip module. For example, two ora few chips 72 and 74 may be mounted on the same side of the ball gridarray substrate 76 as shown in FIG. 7a. The ball grid array 76 is shownattached to the substrate 78. The substrate can be laminated printedcircuit boards, or ceramic, glass, aluminum, copper, or any kind ofsubstrates. FIG. 7b through 7 d illustrate other examples of multiplechip configurations. In all of these examples, more than the two chipsshown can be connected together. The following figures illustrate a“chip-on-chip” structure. It will be understood by those skilled in theart that the present invention should not be limited to any of theexamples shown, but can be extended and applied to any kind of format ofmultiple chip module.

[0029] A “chip-on-chip” structure 300 is shown in FIG. 3. A firstintegrated circuit chip 305 is attached to a second integrated circuitchip 310 by means of an area array of solder bumps 315, for example, asdescribed above. The second integrated circuit chip 310 is securedphysically to the module 320. The electrical connections 325 are eitherwire bonds or TAB bonds. The module 320 has a ball grid array 330 toattach the “chip-on-chip” structure within the module to a next level ofelectronic package. It will be understood that more than two chips maybe connected in this way and that the chips may be connected on the sameside of the ball grid array 330 or on opposite sides.

[0030] The first integrated circuit chip 305 has internal circuits 335,which are the functional electronic components of the first integratedcircuit chip 305. The internal circuits 335 may,be DRAM, logic, or otherintegrated circuits. Likewise, the second integrated circuit chip 310has the internal circuits 365. The internal circuits 365 are thefunctional electronic components of the second integrated circuit chips310. These internal circuits also maybe DRAM, logic, or other integratedcircuits. To transfer signals between the internal circuits 335 of thefirst integrated circuit chip 305 and the internal circuits 365 of thesecond chip 310 or to an external test system, the internal circuits 335are connected to the interchip interface circuits 340. The interchipinterface circuits 340 are connected through the input/output pads 345to the area array of solder bumps 315 and thus to the second chip 310.This connection is functional during multi-chip mode operation, when thefirst integrated circuit chip 305 is mounted to the second integratedcircuit chip 310. These input/output pads 345 have no electrostaticdischarge (ESD) circuits or driving circuits. The input/output pads 345are used in multi-chip modules to bond to other chips, substrates, orother interconnection media.

[0031] For single chip operation mode, the interchip interface circuit340 is bonded to the input/output pads 355 having ESD and drivingcircuits for standalone performance. The bonding may be by wire bonding,solder bumping, or any other interconnection means to a substrate or anyother second level chip carriers. The input/output pads 355 connect tothe input/output or test interface 350.

[0032] The mode select 390 for the first integrated circuit chip 305 isaccomplished by placing an appropriate logic level on the mode selectinput/output pads 391 and 392. When the first integrated circuit chip305 is operating in single-chip mode, the mode select input/output pad391 is brought to a first logic level (0) for stand-alone performance.The system designer could connect the mode selector to an externalsource (such as from a printed circuit board) which can provide logiclevel (0).

[0033] When the first integrated circuit chip 305 is mounted to thesecond integrated circuit chip 310 for multi-chip operation, the modeselect line 390 is brought to a second logic level (1) through the modeselect input/output pad 392. The second logic level (1) is a voltageequal to the power supply voltage source V_(DD) and is achieved byconnecting the mode select input output pad 392 to the mode selectinput/output pad 393 on the second integrated circuit chip 310 throughthe solder ball 394. The mode select input/output pad 393 is connecteddirectly to the power supply voltage source V_(DD) to achieve the secondlogic level (1). When the mode select line 390 is at the second logiclevel (1), the interchip interface 340 transfers signals of the internalcircuits 335 to the input/output pads 345 to the second integratedcircuit chip 310 as described above.

[0034] It should be emphasized that the mode select signal is externalto the chip. During single-chip mode, such as during testing andburn-in, the mode select signal is from the test probe and the burn-insocket, respectively. These signals to the mode select input/output padbring the pad to the first logic level (0), as described above. Afterassembly, when the circuit is in operation, the mode select signal cancome from other chips or from the substrate directly to cause signals ofthe internal circuits to transfer to output pads for one of the otherchips, for example. Alternatively, single-chip operation can still beselected after assembly by setting the mode selector to single chipmode. The advantage of this concept is to extend the application forchips having this inventive design to serve multiple purposes. Thisenhances the commercial value and cost effectiveness of the design.

[0035] The internal circuits 365 of the second integrated circuit chip310 likewise are connected to the interchip interface circuits 360. Theinterchip interface circuits 360 are connected to the input/output pads370 and thus to the first integrated circuit chip 310 through the areaarray of solder bumps 315. The interchip interface circuits 360 areconnected to the I/O or test interface circuits 375.

[0036] The internal circuits 365 of the second integrated circuit chip310 are connected to the input/output interface 385. The input/outputinterface is connected to the input/output pad 395, which is connectedto the module 320 through the bondwire 325. The input/output interfaceprovides the circuitry to transfer signals between the internal circuits365 and the external circuits attached through the next packaging levelto the ball grid array 330 and thus to the wirebond 325.

[0037] The second integrated circuit chip 310 is tested prior toseparation of a wafer containing the second integrated circuit chip 310,by bringing test probes or needles of the test system in contact withthe input/output pads 395 and the test input/output pads 377. Subsequentto dicing of the wafer into individual second integrated circuit chips310, the individual second integrated circuit chips 310 are mounted in aburn-in apparatus. The burn-in apparatus again is brought in contactwith the input/output pads 395 and the test input/output pads 377 toprovide stressing signals to the circuits of the second integratedcircuit chip 310. Then, when the first integrated circuit chip 305 ismounted to the, second integrated circuit chip 310, operation of thewhole “chip-on-chip” assembly 300 is verified by attaching testingprobes or contacts to the ball grid array 330. Signals from the testingprobes are transferred between the circuits of the whole “chip-on-chip”assembly 300 through the bond wires 325 to the input/output pads 395.

[0038] The mode select 380 for the second integrated circuit chip 310 isaccomplished by placing an appropriate logic level on the mode selectinput/output pads 381 and 382. When the second integrated circuit chip310 is in contact with a test system during wafer testing or die testingduring burn-in, the mode select input/output pad 381 is brought to afirst logic level (0) to cause the interchip interface circuit 360 totransfer signals between the internal circuits 365 and the I/O or testinterface 375. The test signals are then transferred between the I/O ortest interface 375 and the test input/output pad 377 as described above.Again, it is noted that the mode select signal comes from outside thechip; from the test probe or burn-in socket, for example, in the testingphase.

[0039] When the first integrated circuit chip 305 is mounted to thesecond integrated circuit chip 310 and multi-chip mode is desired, themode select line 380 is brought to a second logic level (1) through themode select input/output pad 382. The second logic level (1) is achievedby connecting the mode select input output pad 382 to the mode selectinput/output pad 383 on the second integrated circuit chip 310 throughthe solder ball 384. The mode select input/output pad 383 is connecteddirectly to the power supply voltage source V_(DD) to achieve the secondlogic level (1). When the mode select line 380 is at the second logiclevel (1), the interchip interface 360 transfers signals of the internalcircuits 365 to the input/output pads 370 to the first integratedcircuit chip 305 as described above. The mode select signal comes fromthe substrate or from the other chips during operation of the circuit.

[0040] The input/output interface circuit 385 has an input/output buffer389 connected to the internal circuits 365. The input/output buffer 389is either a driver or receiver necessary to translate the signal levelsof the internal circuits 365 to the signal levels of the externalcircuits and the signal levels of the external circuits to the signallevels of the internal circuit 365. The input/output buffer is connectedto the input/output pad 395 and to the ESD protection circuit 387. TheESD protection circuit 387 clamps excess ESD voltages to prevent damageto the input/output buffer 389 and the internal circuits 365 from ESDvoltages brought in contact with the input/output pad 395 from theexternal environment.

[0041]FIGS. 4a through 4 d illustrate a key feature of the presentinvention: to provide two alternative input/output paths. One I/O pathhas an electrostatic discharge (ESD) protection circuit and a drivingcircuit while the other path has no extra loading. One of the two pathsis selected by a mode switch.

[0042]FIGS. 4a and 4 d show schematically the connections of theinterchip interface 340 and the I/O or test interface 350 of the firstintegrated circuit chip 305 of FIG. 3. FIG. 4a illustrates a path of asignal originated within the internal circuits 400 of the firstintegrated circuit chip and FIG. 4d illustrates a path of a signaloriginated externally and received by the internal circuits 462 of thefirst integrated circuit chip.

[0043] Referring now to FIG. 4a, the interchip interface 340 iscomprised of a mode switch 402 and a mode selector 404. The signal 400originating from the internal circuit of the first integrated circuitchip is connected to a first terminal of the mode switch 402. The secondterminal of the mode switch 402 is connected directly to an input/outputpad of the first integrated circuit chip and thus to the internalcircuits of the second integrated circuit chip or other externalcircuits, as described above. The third terminal-of the mode switch 402is connected to the I/O or test interface 350. The I/O or test interfacecircuit 350 is composed of a driver circuit 410 connected toinput/output pad 412 and then to a test probe or burn-in socket or otherexternal probe and to the ESD protection circuit 414. The ESD protectioncircuit 414 operates as the ESD protection circuit 387 of FIG. 3 andclamps excessive ESD voltage to protect the I/O or test interfacecircuit 350 from damage during handling of the wafer containing thefirst integrated circuit chip for manufacturing, assembly, testing, andstand-alone operation.

[0044] The control terminal of the mode switch 402 is connected to amode selector 404 to control the function of the interchip interface340. The signal to the mode selector comes form the substrate, thesecond integrated circuit chip, test probe, burn-in socket, or otherexternal source. When the mode selector 404 is at a first logic state(0), the internal circuits 400 of the first integrated circuit chip areconnected to the I/O or test interface circuit 350. When the modeselector 404 is at a second logic state (1), the internal circuits 400of the first integrated circuit chip are connected to the input/output408 and thus to the internal circuits of the second integrated circuitchip. The mode selector 404 is set to the first state during the testingprocedures of the wafer containing the first integrated circuit chip orduring stand-alone operation. Conversely, when the mode selector 404 isset to the second logic state during the multi-chip mode operation ofthe “chip-on-chip” structure.

[0045] Referring to FIG. 4d, the signals originating in the internalcircuits of the second integrated circuit chip or other external sourceare transferred to the chip pad 454 of the first integrated circuit. Thechip pad 454 is connected to the first terminal of the mode switch 456.The I/O or test interface circuit 350 is connected to the secondterminal of the mode switch 456. The third terminal of the mode switch456 is connected to the internal circuits 462 of the first integratedcircuit chip. The control terminal of the mode switch 456 is connectedto the mode selector 458 to control the function of the interchipinterface 340. The signal to the mode switch comes from the substrate,the second integrated circuit chip, a test probe or burn-in socket, orother external source. If the control terminal of the mode switch 458 isat the first logic state (0), the I/O or test interface circuit 350 isconnected to the internal circuit of the first integrated circuit chip.Conversely, if the control terminal of the mode switch 458 is at thesecond logic state (1), the chip pad 454 of the first integrated circuitchip and thus internal circuits of the second integrated circuit chipare connected to the internal circuits of the first integrated circuitchip.

[0046] As described above, the mode selector 458 is set to the firstlogic state during the testing procedures of the wafer containing thefirst integrated circuit chip or during stand-alone operation and themode selector 458 is set to the second logic state during multi-chipoperation of the “chip-on-chip” structure.

[0047]FIGS. 4b and 4 c show schematically the connections of theinterchip interface 360 and the I/O or I/O or test interface 375 of thesecond integrated circuit chip 310 of FIG. 3. FIG. 4c illustrates a,path of a signal originated within the internal circuits 430 of thesecond integrated circuit chip and FIG. 4b illustrates a path of asignal originated externally and received by the internal circuits 432of the second integrated circuit chip.

[0048]FIG. 4b shows the instance where the signals originate on thefirst integrated circuit chip or other external source and aretransferred through to the input/output pad 422 of the second integratedcircuit chip. The input/output pad 422 is connected to the firstterminal of the mode switch 424. The I/O or test interface circuit 375is connected to the second terminal of the mode switch 424. The thirdterminal of the mode switch 424 is connected to the internal circuits430 of the second integrated circuit chip. The control terminal of themode switch 424 is connected to the mode selector 426, which operates asdescribed above. The signal to the mode selector comes from thesubstrate, the first integrated circuit chip, a test probe or burn-insocket, or other source. If the mode selector is at the first logicstate (0), the test signals from an external test system or other I/Osource are transferred through the I/O or test interface 375 to theinternal circuits 430 of the second integrated circuit chip.Alternatively, if the mode selector 426 is at the second logic state(1), the signals from the internal circuit of the first integratedcircuit chip are connected through the input/output pad 422 to theinternal circuits 430 of the second integrated circuit chip. Again, asdescribed above, the mode selector 426 is set to the first logic stateduring testing procedures or single chip mode operation and is set tothe second logic state during multi-chip mode operation.

[0049] The I/O or test interface is similar to that described in FIG.4d. The test or I/O signals originating in an external test system, suchas from a test probe or burn-in socket or other source, are applied to atest or input/output pad 416. The test or input/output pad 416 isconnected to a receiver 420 and ESD protection circuit 418. The receiver420 translates the test signals to signal levels acceptable by theinternal circuits 430 of the second integrated circuit chip. The ESDprotection circuit 418 clamps ESD voltages applied to the I/O or testpad 416 to prevent damage to the second integrated circuit chip.

[0050]FIG. 4c shows the instance where the signals originate in theinternal circuits 432 of the second integrated circuit chip and aretransferred through chip pad 438 to the first integrated circuit chip.The first terminal of the mode switch 436 receives the signals from theinternal circuits 432 of the second integrated circuit chip. The secondterminal of the mode switch 436 is connected to the chip pad 438. Thethird terminal is connected to the I/O or test interface 375. Thecontrol terminal is connected to the mode selector 434.

[0051] As described above, the mode selector 434, having an input fromthe first integrated circuit chip, the substrate, a test probe, orburn-in socket or other external source, determines the connection ofthe internal circuits 432 to either the chip pad 438 or the I/O or testinterface circuit 375. If the mode selector 434 is set to the firstlogic state (0), the internal circuits 432 are connected to the I/O ortest interface circuit 375, to a test probe or other external source forsingle-chip mode. Alternatively, if the mode selector 434 is at thesecond logic state, the internal circuits 432 are connected through thechip pad 438 to the internal circuits of the first integrated circuitchip or other external location for multi-chip mode.

[0052] The mode selector 434 is set to the first logic state duringsingle chip operation, including testing procedures and to the secondlogic state during multi-chip system operation

[0053]FIGS. 5a and 5 b illustrate the structure of a sample embodimentof the mode switch and the mode selector shown in FIGS. 3 and 4a-d. Itshould be understood by those skilled in the art that the mode switch ofthe present invention should not be limited to the example illustratedin FIGS. 5a through 5 d. It is anticipated that the mode switch can bemade in any number of configurations. The key point of the invention isthe selectable I/O path design concept.

[0054]FIG. 5a shows the mode switch 500 and mode selector 520 forsignals originated from the internal circuits 508 from the first orsecond or other integrated circuit chips. Alternately, FIG. 5b shows themode switch 500 and mode selector 520 for signals originated externallyand transferred to the internal circuits 508 of the first or second orother integrated circuit chips.

[0055] Referring now to FIG. 5a, the first terminal of the mode switch500 is connected to the internal circuits 508, the second terminal ofthe mode switch 500 is connected to the I/O or test interface circuit510 and the third terminal of the mode switch 500 is connected to theinterchip input/output pad 530. Thus, one of two paths may be selectedby the mode switch. The second terminal of the mode switch connects tothe path including a driver circuit 514 and an ESD protection circuit516 to be used for single chip operation. The third terminal connects tothe path to the chip pad 530 having no extra loading to be used formulti-chip operation.

[0056] The mode switch is comprised of the pass switches 502 and 504 andinverter 506. The pass switch 502 is the parallel combination of then-channel metal oxide semiconductor (NMOS) transistor 502 a andp-channel metal oxide semiconductor (PMOS) transistor 502 b. Likewise,the pass switch 504 is the parallel combination of the NMOS transistor504 a and the PMOS transistor 504 b. The first terminal of the modeswitch 500 and thus the internal circuits 508 are connected to thedrains of the pass switches 502 and 504. The sources of the pass switch502 are connected to the third terminal of the mode switch 500 and thusto the interchip input/output pad 530. The sources of the pass switch504 are connected to the second terminal of the mode switch 500 and thusto the I/O or test interface circuit 510. The gates of the NMOStransistor 504 a and the PMOS transistor 502 b are connected to theoutput of the inverter 506. The gates of the NMOS transistor 502 a, PMOStransistor 504 b, and the input of the inverter 506 are connected to thecontrol terminal of the mode switch 500 and thus to the mode selector520.

[0057] An ESD protection circuit 507 is added to prevent damage to themode switch during testing and assembly. After the chip is assembled,the ESD protection circuit will not influence performance of the chip.

[0058] When the control terminal of the mode switch 500 is at the firstlogic state (0), in this case a voltage level approaching that of thesubstrate biasing voltage source V_(SS), the pass switch 504 is turnedon and the pass switch 502 is turned off. The internal circuits are nowset for single chip operation; for example, the internal circuits may beeffectively connected to the I/O or test interface circuit 510.Conversely, when the control terminal of the mode switch 500 is at thesecond logic state, in this case a voltage level approaching that of thepower supply voltage source V_(DD), the pass switch 502 is turned on andthe pass switch 504 is turned off. This effectively connects theinternal circuits 508 to the interchip input/output pad 530. In thislogic state, the extra electrical load is from the drain of the passswitch 502 and the pass switch 504. This electrical load is very smalland thus highly improved performance can be expected over the prior art.

[0059] The I/O or test interface circuit 510 is comprised of the drivercircuit 514 and the ESD protection circuit 516: The I/O or testinterface circuit functions as described in FIGS. 4a and 4 c.

[0060] The mode select circuit is the interchip input/output pad 522 andthe I/O or test input/output pad 524 connected together and to thecontrol terminal of the mode switch 500. The interchip input/output pad522 is connected as described in FIG. 3 to a mating interchipinput/output pad 562 that are joined by a solder bump or ball. Themating interchip input/output pad 562 is on the mating chip 560 and isconnected to the power supply voltage source V_(DD) to provide thesecond logic state to the control terminal of the mode switch 500 duringmultichip mode operation. The I/O or test input/output pad is connectedto an external source 550 during single chip operation. For example,during testing, a test probe or needle 552 is brought in contact withthe test input/output pad. The test probe or needle 552 is connected ona probe card 554 within the test system 550 to the substrate biasingvoltage source V_(SS) to provide the first logic state to the controlterminal of the mode switch 500. The external source 550 could also befrom a substrate or a printed circuit board, and so on.

[0061] The fundamental connections shown in FIG. 5b are as described inFIG. 5a except the I/O signal originates from an external systemattached to the input/output pad 540. The I/O or test interface circuit510 in this case is comprised of the receiver 518 and the ESD protectioncircuit and functions as described in FIGS. 4b and 4 d.

[0062] Signals originating from the external circuits are applied to theinterchip input/output pad 530 and transferred through the pass switch502 to the internal circuits 508 during multi-chip mode operation.Likewise, the external signals are transferred from the I/O or testinterface 510 through the pass switch 504 to the internal circuits 508during single chip operation.

[0063] It is preferred not to have ESD protection on node 3 of thecircuit connected to the, input/output pad 530 because ESD loading willimpact chip performance after assembly. However, ESD may impact thisnode during testing and assembly, for example. Therefore, a small ESDprotection circuit 532 may be added on this node, as shown in FIG. 5c(corresponding to FIG. 5a) and FIG. 5d (corresponding to FIG. 5b).

[0064]FIG. 6a shows a top surface view of the first integrated circuitchip 600 illustrating the placement of the test input/output pads 605and the interchip input/output pads 610. The interchip input/output pads610 form an area array of solder balls or bumps 315 of FIG. 3. The I/Oor test input/output pads 605 are peripherally arranged so that the testprobes or needles of the test system can conveniently make contact withthe test input/output pads 605.

[0065]FIG. 6b shows the top surface view of the second integratedcircuit chip 615 illustrating the placement of the interchipinput/output pads 625 and the external input/output pads 620. Theinterchip input/output pads 625 form the area array to mate with theinterchip input/output pads 610 of FIG. 5a. The first integrated circuitchip 600 is mounted “face-to face” to the second integrated circuit chip615. The test input/output pads 605 must have nothing on the surface ofthe second integrated circuit chip 625 in their “shadow.”

[0066] The test input/output pads 630 and the external input/output pads620 are formed in the periphery of the second integrated circuit chip615. The external input/output pads 620 must be placed outside theshadow of the first integrated circuit chip 600. The test input/outputpads 630 are placed conveniently so that test probes or needles of atest system can contact the test input/output pads 630. The testinput/output pads 605 and 630 are connected as shown in FIGS. 5a and 5 bto the I/O or test interface 510. The test input/output pads 605 and 630transfer stimulus and response signals between the test system 550 andeither the first integrated circuit chip 600 or second integratedcircuit chip 615.

[0067] While this invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

The invention claimed is:
 1. A multiple interconnected integratedcircuit chip structure comprising a first integrated circuit chip andone or more second integrated circuit chips comprising: whereby saidfirst integrated circuit chip is physically and electrically connectedto said one or more second integrated circuit chips; whereby said firstintegrated circuit chip has interchip interface circuits connected tosaid one or more second integrated circuit chips to selectivelycommunicate between internal circuits of said first and secondintegrated circuit chips and input/output circuits connected to internalcircuits of the first integrated circuit chip to provide stimulus andresponse to said internal circuits; whereby each of said secondintegrated circuit chips has input/output interface circuitry tocommunicate with external circuitry connected to said second integratedcircuit chip and to protect said second integrated circuit chip fromelectrostatic discharge voltages; whereby the interchip interfacecircuitry comprises: an internal interface circuit for transferringelectrical signals between each of said second integrated circuit chipsand said first integrated circuit chip; a mode select switch having afirst terminal connected to an input/output pad, a second terminalconnected to the internal circuitry of said first integrated circuitchip, and a third terminal connected to input/output circuits, and amode selector to selectively connect the output of the internalinterface circuit to the internal circuitry of the first integratedcircuit chip during multi-chip operation and the output of the internalinterface circuit to the input/output circuitry during single chipoperation.
 2. The chip structure of claim 1 wherein each of said secondintegrated circuit chips further has interchip interface circuitsconnected to said first integrated circuit chip to selectivelycommunicate between internal circuits of the first and second integratedcircuit chips and input/output circuits connected to internal circuitsof the second integrated circuit chip to provide stimulus and responseto said internal circuits.
 3. The chip structure of claim 1 wherein eachof said second integrated circuit chips further has interchip interfacecircuits connected to each of the other said second integrated circuitchips to selectively communicate between internal circuits of each ofsaid second integrated circuit chips and input/output circuits connectedto internal circuits each of each second integrated circuit chips toprovide stimulus and response to said internal circuits.
 4. The chipstructure of claim 1 wherein said first integrated circuit chip isphysically connected to each of said second integrated circuit chips byan interconnection means wherein said first and second integratedcircuit chips are mounted on one or more of the following: the same sideof said interconnection means, opposite sides of said interconnectionmeans.
 5. The chip structure of claim 1 wherein the input/outputcircuits comprise: connection to an external input/output source; andESD protection circuits to protect said first and second integratedcircuit chips from electrostatic discharge voltages.
 6. The chipstructure of claim 5 wherein said external input/output source comprisesexternal test circuitry temporarily connected during test and burn-in.7. The chip structure of claim 1 wherein the interchip interface circuithas no electrostatic discharge protection circuit.
 8. The chip structureof claim 1 wherein the interchip interface circuit has an electrostaticdischarge protection circuit.
 9. The chip structure of claim 1 whereinthe mode switch comprises: a first pass switch having a drain terminalconnected to the internal circuits, a source terminal connected to aninput/output pad connected to an attached integrated circuit chip, afirst gate terminal connected to the mode selector, and a second gateterminal; a second pass switch having a drain terminal connected to theinternal circuits, a source terminal connected to the input/output padconnected to the attached integrated circuit chip, a first gateterminal, and a second gate terminal connected to the mode selector; aninverter circuit having an input terminal connected to the mode selectorand an output terminal connected to the second gate terminal of thefirst pass switch and the first gate of the second pass switch; and anelectrostatic discharge protection circuit.
 10. The chip structure ofclaim 9 wherein the first and second pass switches are comprised of anNMOS transistor and PMOS transistor connected in parallel with a gate ofthe NMOS transistor being the first gate terminal of the first andsecond pass switches and a gate of the PMOS transistor being the secondgate terminal of the first and second pass switches.
 11. The chipstructure of claim 1 wherein the mode switch comprises: a first passswitch having a drain terminal connected to the internal circuits, asource terminal connected to an input/output pad connected to anattached integrated circuit chip, a first gate terminal connected to themode selector, and a second gate terminal; a second pass switch having adrain terminal connected to the internal circuits, a source terminalconnected to the input/output pad connected to the attached integratedcircuit chip, an electrostatic discharge protection circuit attached tosaid input/output pad, a first gate terminal, and a second gate terminalconnected to the mode selector; an inverter circuit having an inputterminal connected to the mode selector and an output terminal connectedto the second gate terminal of the first pass switch and the first gateof the second pass switch; and an electrostatic discharge protectioncircuit.
 12. The chip structure of claim 11 wherein the first and secondpass switches are comprised of an NMOS transistor and PMOS transistorconnected in parallel with a gate of the NMOS transistor being the firstgate terminal of the first and second pass switches and a gate of thePMOS transistor being the second gate terminal of the first and secondpass switches.
 13. The chip structure of claim 1 wherein the mode switchcomprises: an input/output pad connected to a first logic stategenerator during single chip operation; and an interchip input/outputpad connected to a second logic state generator during multi-chipoperation.
 14. The mode switch of claim 13 wherein said single chipoperation is a test operation and wherein said input/output pad is atest input/output pad.
 15. The mode selector of claim 1 wherein a modeselect signal is input to said mode selector from one of the following:said first integrated circuit chip, one of said plurality of secondintegrated circuit chips, a test interface, and another external source.16. The chip structure of claim 1 wherein each of said first and secondintegrated circuit chips can be set to operate in single chip mode or inmulti-chip mode via said mode selector.
 17. An interchip interfacecircuit formed in multiples upon a plurality of integrated circuit chipsfor communication between internal circuits of the plurality ofintegrated circuit chips; whereby said plurality of integrated circuitchips are attached physically and electrically to one another; andwhereby each interchip interface circuit comprises: an internalinterface circuit for transferring electrical signals between a one ofsaid integrated circuit chips to another of said integrated circuitchips; a mode select switch having a first terminal connected to anoutput of the internal interface circuit, a second terminal connected tothe internal circuitry said one of said integrated circuit chips, athird terminal connected to I/O circuits, and a control terminal; and amode selector connected to the control terminal to selectively connectthe output of the internal interface circuit to the internal circuitryof said one of said integrated circuit chips during multi-chip operationand the output of the internal interface circuit to I/O interfacecircuitry during single chip operation.
 18. The interface circuit ofclaim 17 wherein said plurality of integrated circuit chips are attachedto one or more substrates by an interconnection means.
 19. The interfacecircuit of claim 18 wherein said substrates are selected from the groupconsisting of: printed circuit boards, ceramic substrates, glasssubstrates, aluminum substrates, and copper substrates and wherein saidplurality of integrated circuit chips are attached on one side oropposite sides of said interconnection means.
 20. The interface circuitof claim 17 wherein said I/O interface circuitry comprises: testinterface circuits connected to external test circuitry to communicatewith said external test circuitry; and an ESD protection circuit toprotect said plurality of integrated circuit chips from electrostaticdischarge voltages.
 21. The interface circuit of claim 20 wherein thetest interface circuit is connected to the external test circuitrythrough an input/output pad temporarily connected to said external testcircuitry during test and burn-in.
 22. The interface circuit of claim 17wherein said I/O interface circuitry comprises: connection to anexternal I/O source; and an ESD protection circuit to protect saidplurality of integrated circuit chips from electrostatic dischargevoltages
 23. The interface circuit of claim 17 wherein the interchipinterface circuit has no electrostatic discharge protection circuit. 24.The interface circuit of claim 17 wherein the interchip interfacecircuit has an electrostatic discharge protection circuit.
 25. Theinterface circuit of claim 17 wherein the mode switch comprises: a firstpass switch having a drain terminal connected to the internal circuits,a source terminal connected to an input/output pad connected to anattached integrated circuit chip, a first gate terminal connected to themode selector, and a second gate terminal; a second pass switch having adrain terminal connected to the internal circuits, a source terminalconnected to the input/output pad connected to the attached integratedcircuit chip, a first gate terminal, and a second gate terminalconnected to the mode selector; an inverter circuit having an inputterminal connected to the mode selector and an output terminal connectedto the second gate terminal of the first pass switch and the first gateof the second pass switch; and an electrostatic discharge protectioncircuit.
 26. The interface circuit of claim 25 wherein the first andsecond pass switches are comprised of an NMOS transistor and PMOStransistor connected in parallel with a gate of the NMOS transistorbeing the first gate terminal of the first and second pass switches anda gate of the PMOS transistor being the second gate terminal of thefirst and second pass switches.
 27. The interface circuit of claim 17wherein the mode switch comprises: a first pass switch having a drainterminal connected to the internal circuits, a source terminal connectedto an input/output pad connected to an attached integrated circuit chip,a first gate terminal connected to the mode selector, and a second gateterminal; a second pass switch having a drain terminal connected to theinternal circuits, a source terminal connected to the input/output padconnected to the attached integrated circuit chip, an electrostaticdischarge protection circuit attached to said input/output pad, a firstgate terminal, and a second gate terminal connected to the modeselector; an inverter circuit having an input terminal connected to themode selector and an output terminal connected to the second gateterminal of the first pass switch and the first gate of the second passswitch; and an electrostatic discharge protection circuit.
 28. Theinterface circuit of claim 27 wherein the first and second pass switchesare comprised of an NMOS transistor and PMOS transistor connected inparallel with a gate of the NMOS transistor being the first gateterminal of the first and second pass switches and a gate of the PMOStransistor being the second gate terminal of the first and second passswitches.
 29. The interface circuit of claim 17 wherein in the modeswitch comprises: an I/O or test input/output pad connected to a firstlogic state generator during single chip mode operation; and aninterchip input/output pad connected to a second logic state generatorduring multi-chip mode operation;
 30. The mode selector of claim 17wherein a mode select signal is input to said mode selector from one ofthe following: said first integrated circuit chip, one of said pluralityof second-integrated circuit chips, a test interface, and anotherexternal source.
 31. A method of forming a multiple integrated circuitchip structure comprising the steps of: simultaneously but separatelyforming internal circuits on a plurality of semiconductor waferscontaining a plurality of integrated circuit chips; simultaneouslyforming input/output circuits on said plurality of semiconductor wafers;simultaneously forming interchip interface circuits on said plurality ofsemiconductor wafers, whereby forming said interchip interface circuitcomprises the steps of: forming an internal interface circuit fortransferring electrical signals between each of said plurality ofintegrated circuit chips to each other of said integrated circuit chips;forming a mode select switch having a first terminal connected to anoutput of the internal interface circuit and a second terminal connectedto the internal circuitry of one of said plurality of integrated circuitchips; forming a mode selector to selectively connect the output of theinternal interface circuit to the internal circuitry of said one of saidintegrated circuit chips during multi-chip operation and the output ofthe internal interface circuit to the input/output circuits duringsingle chip operation; during single chip operation, contacting,stimulating, and examining a response of test circuits connected to saidinput/output circuitry and input/output interface circuits on the saidplurality of wafers; separating said plurality of semiconductor wafersinto a plurality of separated integrated circuit chips; contacting withsockets, stimulating and burning-in the plurality of separatedintegrated circuit chips for an extended period of time; contacting,stimulating, and examining the plurality of separated integrated circuitchips; discarding defective integrated circuit chips; attaching eachfunctioning chip of one of said semiconductor wafers to one or morefunctioning chips of one or more of other of said plurality ofsemiconductor wafers; and contacting the input/output interfacecircuits, stimulating, and examining the response of the formed multipleintegrated circuit chip structure.
 32. The method of claim 31 whereinthe attaching of each of said integrated circuit chips of one of saidsemiconductor wafers to said one or more chips of said one or more ofsaid other of said plurality of semiconductor wafers is accomplished byforming an interconnection means between each of the plurality ofintegrated circuit chips wherein said plurality of integrated circuitchips may be attached on one side and/or on opposite sides of saidinterconnection means.
 33. The method of claim 31 wherein said formingsaid input/output circuits comprises the steps of: forming I/O or testinterface circuits connected to external I/O sources; and forming ESDprotection circuitry to protect said first and second integrated circuitchips from electrostatic discharge voltages.
 34. The method of claim 31wherein said plurality of integrated circuit chips on each of saidplurality of semiconductor wafers are fabricated using a different typesof semiconductor processes.
 35. The method of claim 33 whereincontacting said I/O or test interface circuit comprises temporarilyconnecting external test circuitry through an input/output pad to saidI/O or test interface circuit.
 36. The method of claim 31 wherein theinterchip interface circuit is formed with no electrostatic dischargeprotection circuit.
 37. The method of claim 31 wherein the interchipinterface circuit is formed with an electrostatic discharge protectioncircuit.
 38. The method of claim 31 wherein the mode switch comprises: afirst pass switch having a drain terminal connected to the internalcircuits, a source terminal connected to an input/output pad connectedto an attached integrated circuit chip, a first gate terminal connectedto the mode selector, and a second gate terminal; a second pass switchhaving a drain terminal connected to the internal circuits, a sourceterminal connected to the input/output pad connected to the attachedintegrated circuit chip, a first gate terminal, and a second gateterminal connected to the mode selector; an inverter circuit having aninput terminal connected to the mode selector and an output terminalconnected to the second gate terminal of the first pass switch and thefirst gate of the second pass switch; and an electrostatic dischargeprotection circuit.
 39. The method of claim 38 wherein the first andsecond pass switches are comprised of an NMOS transistor and PMOStransistor connected in parallel with a gate of the NMOS transistorbeing the first gate terminal of the first and second pass switches anda gate of the PMOS transistor being the second gate terminal of thefirst and second pass switches.
 40. The method of claim 31 wherein themode switch comprises: a first pass switch having a drain terminalconnected to the internal circuits, a source terminal connected to aninput/output pad connected to an attached integrated circuit chip, afirst gate terminal connected to the mode selector, and a second gateterminal; a second pass switch having a drain terminal connected to theinternal circuits, a source terminal connected to the input/output padconnected to the attached integrated circuit chip, an electrostaticdischarge protect:ion circuit attached to said input/output pad, a firstgate terminal, and a second gate terminal connected to the modeselector; an inverter circuit having an input terminal connected to themode selector and an output terminal connected to the second gateterminal of the first pass switch and the first gate of the second passswitch; and an electrostatic discharge protection circuit.
 41. Themethod of claim 40 wherein the first and second pass switches arecomprised of an NMOS transistor and PMOS transistor connected inparallel with a gate of the NMOS transistor being the first gateterminal of the first and second pass switches and a gate of the PMOStransistor being the second gate terminal of the first and second passswitches.
 42. The method of claim 31 wherein in the mode switchcomprises: an I/O or test input/output pad connected to a first logicstate generator during single chip mode operation; and an interchipinput/output pad connected to a second logic state generator duringmulti-chip mode operation;
 43. The method of claim 31 wherein a modeselect signal is input to said mode selector from one of the following:said first integrated circuit chip, one of said plurality of secondintegrated circuit chips, a test interface, and another external source.